-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"

-- DATE "11/25/2023 17:38:05"

-- 
-- Device: Altera EP4CE6E22C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	lab2_fre_div4_021 IS
    PORT (
	B2_021 : OUT std_logic;
	CLK_021 : IN std_logic;
	pin_name1 : OUT std_logic;
	pin_name2 : OUT std_logic
	);
END lab2_fre_div4_021;

-- Design Ports Information
-- B2_021	=>  Location: PIN_1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- pin_name1	=>  Location: PIN_28,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- pin_name2	=>  Location: PIN_30,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- CLK_021	=>  Location: PIN_23,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF lab2_fre_div4_021 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_B2_021 : std_logic;
SIGNAL ww_CLK_021 : std_logic;
SIGNAL ww_pin_name1 : std_logic;
SIGNAL ww_pin_name2 : std_logic;
SIGNAL \B2_021~output_o\ : std_logic;
SIGNAL \pin_name1~output_o\ : std_logic;
SIGNAL \pin_name2~output_o\ : std_logic;
SIGNAL \CLK_021~input_o\ : std_logic;
SIGNAL \inst|inst3|inst|7~0_combout\ : std_logic;
SIGNAL \inst|inst3|inst|7~q\ : std_logic;
SIGNAL \inst|inst3|inst|20~combout\ : std_logic;
SIGNAL \inst|inst3|inst|6~0_combout\ : std_logic;
SIGNAL \inst|inst3|inst|6~q\ : std_logic;
SIGNAL \inst|inst3|inst|5~0_combout\ : std_logic;
SIGNAL \inst|inst3|inst|5~q\ : std_logic;
SIGNAL \inst|inst3|inst|3~0_combout\ : std_logic;
SIGNAL \inst|inst3|inst|3~feeder_combout\ : std_logic;
SIGNAL \inst|inst3|inst|3~q\ : std_logic;
SIGNAL \inst|inst3|inst|34~0_combout\ : std_logic;
SIGNAL \inst|inst3|inst|34~q\ : std_logic;
SIGNAL \inst|inst3|inst|29~combout\ : std_logic;
SIGNAL \inst|inst3|inst|33~0_combout\ : std_logic;
SIGNAL \inst|inst3|inst|33~q\ : std_logic;
SIGNAL \inst|inst3|inst|32~0_combout\ : std_logic;
SIGNAL \inst|inst3|inst|32~q\ : std_logic;
SIGNAL \inst|inst3|inst|31~0_combout\ : std_logic;
SIGNAL \inst|inst3|inst|31~q\ : std_logic;
SIGNAL \inst|inst1|inst|7~0_combout\ : std_logic;
SIGNAL \inst|inst1|inst|7~q\ : std_logic;
SIGNAL \inst|inst1|inst|20~combout\ : std_logic;
SIGNAL \inst|inst1|inst|6~0_combout\ : std_logic;
SIGNAL \inst|inst1|inst|6~q\ : std_logic;
SIGNAL \inst|inst1|inst|5~0_combout\ : std_logic;
SIGNAL \inst|inst1|inst|5~q\ : std_logic;
SIGNAL \inst|inst1|inst|3~0_combout\ : std_logic;
SIGNAL \inst|inst1|inst|3~q\ : std_logic;
SIGNAL \inst|inst1|inst|34~0_combout\ : std_logic;
SIGNAL \inst|inst1|inst|34~q\ : std_logic;
SIGNAL \inst|inst1|inst|29~combout\ : std_logic;
SIGNAL \inst|inst1|inst|33~0_combout\ : std_logic;
SIGNAL \inst|inst1|inst|33~q\ : std_logic;
SIGNAL \inst|inst1|inst|32~0_combout\ : std_logic;
SIGNAL \inst|inst1|inst|32~q\ : std_logic;
SIGNAL \inst|inst1|inst|31~0_combout\ : std_logic;
SIGNAL \inst|inst1|inst|31~q\ : std_logic;
SIGNAL \inst|inst2|inst|20~combout\ : std_logic;
SIGNAL \inst|inst2|inst|6~0_combout\ : std_logic;
SIGNAL \inst|inst2|inst|6~q\ : std_logic;
SIGNAL \inst|inst2|inst|5~0_combout\ : std_logic;
SIGNAL \inst|inst2|inst|5~q\ : std_logic;
SIGNAL \inst|inst2|inst|3~0_combout\ : std_logic;
SIGNAL \inst|inst2|inst|3~q\ : std_logic;
SIGNAL \inst|inst2|inst|7~0_combout\ : std_logic;
SIGNAL \inst|inst2|inst|7~q\ : std_logic;
SIGNAL \inst1~combout\ : std_logic;
SIGNAL \ALT_INV_CLK_021~input_o\ : std_logic;
SIGNAL \inst|inst3|inst|ALT_INV_7~q\ : std_logic;
SIGNAL \inst|inst3|inst|ALT_INV_6~q\ : std_logic;
SIGNAL \inst|inst3|inst|ALT_INV_3~q\ : std_logic;
SIGNAL \inst|inst3|inst|ALT_INV_34~q\ : std_logic;
SIGNAL \inst|inst3|inst|ALT_INV_33~q\ : std_logic;
SIGNAL \inst|inst3|inst|ALT_INV_31~q\ : std_logic;
SIGNAL \inst|inst1|inst|ALT_INV_7~q\ : std_logic;
SIGNAL \inst|inst1|inst|ALT_INV_6~q\ : std_logic;
SIGNAL \inst|inst2|inst|ALT_INV_6~q\ : std_logic;
SIGNAL \inst|inst1|inst|ALT_INV_3~q\ : std_logic;
SIGNAL \inst|inst2|inst|ALT_INV_3~q\ : std_logic;
SIGNAL \inst|inst1|inst|ALT_INV_34~q\ : std_logic;
SIGNAL \inst|inst1|inst|ALT_INV_33~q\ : std_logic;
SIGNAL \inst|inst1|inst|ALT_INV_31~q\ : std_logic;

BEGIN

B2_021 <= ww_B2_021;
ww_CLK_021 <= CLK_021;
pin_name1 <= ww_pin_name1;
pin_name2 <= ww_pin_name2;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_CLK_021~input_o\ <= NOT \CLK_021~input_o\;
\inst|inst3|inst|ALT_INV_7~q\ <= NOT \inst|inst3|inst|7~q\;
\inst|inst3|inst|ALT_INV_6~q\ <= NOT \inst|inst3|inst|6~q\;
\inst|inst3|inst|ALT_INV_3~q\ <= NOT \inst|inst3|inst|3~q\;
\inst|inst3|inst|ALT_INV_34~q\ <= NOT \inst|inst3|inst|34~q\;
\inst|inst3|inst|ALT_INV_33~q\ <= NOT \inst|inst3|inst|33~q\;
\inst|inst3|inst|ALT_INV_31~q\ <= NOT \inst|inst3|inst|31~q\;
\inst|inst1|inst|ALT_INV_7~q\ <= NOT \inst|inst1|inst|7~q\;
\inst|inst1|inst|ALT_INV_6~q\ <= NOT \inst|inst1|inst|6~q\;
\inst|inst2|inst|ALT_INV_6~q\ <= NOT \inst|inst2|inst|6~q\;
\inst|inst1|inst|ALT_INV_3~q\ <= NOT \inst|inst1|inst|3~q\;
\inst|inst2|inst|ALT_INV_3~q\ <= NOT \inst|inst2|inst|3~q\;
\inst|inst1|inst|ALT_INV_34~q\ <= NOT \inst|inst1|inst|34~q\;
\inst|inst1|inst|ALT_INV_33~q\ <= NOT \inst|inst1|inst|33~q\;
\inst|inst1|inst|ALT_INV_31~q\ <= NOT \inst|inst1|inst|31~q\;

-- Location: IOOBUF_X0_Y23_N2
\B2_021~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst1~combout\,
	devoe => ww_devoe,
	o => \B2_021~output_o\);

-- Location: IOOBUF_X0_Y9_N9
\pin_name1~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|inst1|inst|31~q\,
	devoe => ww_devoe,
	o => \pin_name1~output_o\);

-- Location: IOOBUF_X0_Y8_N16
\pin_name2~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|inst2|inst|7~q\,
	devoe => ww_devoe,
	o => \pin_name2~output_o\);

-- Location: IOIBUF_X0_Y11_N8
\CLK_021~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_CLK_021,
	o => \CLK_021~input_o\);

-- Location: LCCOMB_X8_Y8_N28
\inst|inst3|inst|7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|7~0_combout\ = !\inst|inst3|inst|7~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst3|inst|7~q\,
	combout => \inst|inst3|inst|7~0_combout\);

-- Location: FF_X8_Y8_N29
\inst|inst3|inst|7\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \ALT_INV_CLK_021~input_o\,
	d => \inst|inst3|inst|7~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst3|inst|7~q\);

-- Location: LCCOMB_X8_Y8_N30
\inst|inst3|inst|20\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|20~combout\ = LCELL((\inst|inst3|inst|3~q\) # (!\inst|inst3|inst|7~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst3|inst|3~q\,
	datad => \inst|inst3|inst|7~q\,
	combout => \inst|inst3|inst|20~combout\);

-- Location: LCCOMB_X10_Y7_N4
\inst|inst3|inst|6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|6~0_combout\ = !\inst|inst3|inst|6~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst3|inst|6~q\,
	combout => \inst|inst3|inst|6~0_combout\);

-- Location: FF_X10_Y7_N5
\inst|inst3|inst|6\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst3|inst|20~combout\,
	d => \inst|inst3|inst|6~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst3|inst|6~q\);

-- Location: LCCOMB_X10_Y7_N10
\inst|inst3|inst|5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|5~0_combout\ = !\inst|inst3|inst|5~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst3|inst|5~q\,
	combout => \inst|inst3|inst|5~0_combout\);

-- Location: FF_X10_Y7_N11
\inst|inst3|inst|5\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst3|inst|ALT_INV_6~q\,
	d => \inst|inst3|inst|5~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst3|inst|5~q\);

-- Location: LCCOMB_X10_Y7_N0
\inst|inst3|inst|3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|3~0_combout\ = (\inst|inst3|inst|6~q\ & (!\inst|inst3|inst|3~q\ & \inst|inst3|inst|5~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|inst3|inst|6~q\,
	datac => \inst|inst3|inst|3~q\,
	datad => \inst|inst3|inst|5~q\,
	combout => \inst|inst3|inst|3~0_combout\);

-- Location: LCCOMB_X8_Y8_N22
\inst|inst3|inst|3~feeder\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|3~feeder_combout\ = \inst|inst3|inst|3~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \inst|inst3|inst|3~0_combout\,
	combout => \inst|inst3|inst|3~feeder_combout\);

-- Location: FF_X8_Y8_N23
\inst|inst3|inst|3\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst3|inst|ALT_INV_7~q\,
	d => \inst|inst3|inst|3~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst3|inst|3~q\);

-- Location: LCCOMB_X6_Y8_N8
\inst|inst3|inst|34~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|34~0_combout\ = !\inst|inst3|inst|34~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst3|inst|34~q\,
	combout => \inst|inst3|inst|34~0_combout\);

-- Location: FF_X6_Y8_N9
\inst|inst3|inst|34\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst3|inst|ALT_INV_3~q\,
	d => \inst|inst3|inst|34~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst3|inst|34~q\);

-- Location: LCCOMB_X6_Y8_N6
\inst|inst3|inst|29\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|29~combout\ = LCELL((\inst|inst3|inst|31~q\) # (!\inst|inst3|inst|34~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst3|inst|34~q\,
	datad => \inst|inst3|inst|31~q\,
	combout => \inst|inst3|inst|29~combout\);

-- Location: LCCOMB_X7_Y8_N4
\inst|inst3|inst|33~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|33~0_combout\ = !\inst|inst3|inst|33~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst3|inst|33~q\,
	combout => \inst|inst3|inst|33~0_combout\);

-- Location: FF_X7_Y8_N5
\inst|inst3|inst|33\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst3|inst|29~combout\,
	d => \inst|inst3|inst|33~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst3|inst|33~q\);

-- Location: LCCOMB_X7_Y8_N6
\inst|inst3|inst|32~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|32~0_combout\ = !\inst|inst3|inst|32~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst3|inst|32~q\,
	combout => \inst|inst3|inst|32~0_combout\);

-- Location: FF_X7_Y8_N7
\inst|inst3|inst|32\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst3|inst|ALT_INV_33~q\,
	d => \inst|inst3|inst|32~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst3|inst|32~q\);

-- Location: LCCOMB_X6_Y8_N20
\inst|inst3|inst|31~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst3|inst|31~0_combout\ = (\inst|inst3|inst|33~q\ & (!\inst|inst3|inst|31~q\ & \inst|inst3|inst|32~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|inst3|inst|33~q\,
	datac => \inst|inst3|inst|31~q\,
	datad => \inst|inst3|inst|32~q\,
	combout => \inst|inst3|inst|31~0_combout\);

-- Location: FF_X6_Y8_N21
\inst|inst3|inst|31\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst3|inst|ALT_INV_34~q\,
	d => \inst|inst3|inst|31~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst3|inst|31~q\);

-- Location: LCCOMB_X18_Y13_N14
\inst|inst1|inst|7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|7~0_combout\ = !\inst|inst1|inst|7~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|7~q\,
	combout => \inst|inst1|inst|7~0_combout\);

-- Location: FF_X18_Y13_N15
\inst|inst1|inst|7\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst3|inst|ALT_INV_31~q\,
	d => \inst|inst1|inst|7~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst1|inst|7~q\);

-- Location: LCCOMB_X18_Y13_N16
\inst|inst1|inst|20\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|20~combout\ = LCELL((\inst|inst1|inst|3~q\) # (!\inst|inst1|inst|7~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|7~q\,
	datad => \inst|inst1|inst|3~q\,
	combout => \inst|inst1|inst|20~combout\);

-- Location: LCCOMB_X23_Y16_N8
\inst|inst1|inst|6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|6~0_combout\ = !\inst|inst1|inst|6~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|6~q\,
	combout => \inst|inst1|inst|6~0_combout\);

-- Location: FF_X23_Y16_N9
\inst|inst1|inst|6\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst1|inst|20~combout\,
	d => \inst|inst1|inst|6~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst1|inst|6~q\);

-- Location: LCCOMB_X23_Y16_N4
\inst|inst1|inst|5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|5~0_combout\ = !\inst|inst1|inst|5~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|5~q\,
	combout => \inst|inst1|inst|5~0_combout\);

-- Location: FF_X23_Y16_N5
\inst|inst1|inst|5\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst1|inst|ALT_INV_6~q\,
	d => \inst|inst1|inst|5~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst1|inst|5~q\);

-- Location: LCCOMB_X18_Y13_N28
\inst|inst1|inst|3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|3~0_combout\ = (\inst|inst1|inst|6~q\ & (!\inst|inst1|inst|3~q\ & \inst|inst1|inst|5~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|inst1|inst|6~q\,
	datac => \inst|inst1|inst|3~q\,
	datad => \inst|inst1|inst|5~q\,
	combout => \inst|inst1|inst|3~0_combout\);

-- Location: FF_X18_Y13_N29
\inst|inst1|inst|3\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst1|inst|ALT_INV_7~q\,
	d => \inst|inst1|inst|3~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst1|inst|3~q\);

-- Location: LCCOMB_X18_Y11_N28
\inst|inst1|inst|34~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|34~0_combout\ = !\inst|inst1|inst|34~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|34~q\,
	combout => \inst|inst1|inst|34~0_combout\);

-- Location: FF_X18_Y11_N29
\inst|inst1|inst|34\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst1|inst|ALT_INV_3~q\,
	d => \inst|inst1|inst|34~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst1|inst|34~q\);

-- Location: LCCOMB_X18_Y11_N16
\inst|inst1|inst|29\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|29~combout\ = LCELL((\inst|inst1|inst|31~q\) # (!\inst|inst1|inst|34~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|31~q\,
	datad => \inst|inst1|inst|34~q\,
	combout => \inst|inst1|inst|29~combout\);

-- Location: LCCOMB_X17_Y13_N10
\inst|inst1|inst|33~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|33~0_combout\ = !\inst|inst1|inst|33~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|33~q\,
	combout => \inst|inst1|inst|33~0_combout\);

-- Location: FF_X17_Y13_N11
\inst|inst1|inst|33\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst1|inst|29~combout\,
	d => \inst|inst1|inst|33~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst1|inst|33~q\);

-- Location: LCCOMB_X17_Y13_N4
\inst|inst1|inst|32~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|32~0_combout\ = !\inst|inst1|inst|32~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|32~q\,
	combout => \inst|inst1|inst|32~0_combout\);

-- Location: FF_X17_Y13_N5
\inst|inst1|inst|32\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst1|inst|ALT_INV_33~q\,
	d => \inst|inst1|inst|32~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst1|inst|32~q\);

-- Location: LCCOMB_X18_Y11_N30
\inst|inst1|inst|31~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst1|inst|31~0_combout\ = (\inst|inst1|inst|32~q\ & (\inst|inst1|inst|33~q\ & !\inst|inst1|inst|31~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \inst|inst1|inst|32~q\,
	datab => \inst|inst1|inst|33~q\,
	datac => \inst|inst1|inst|31~q\,
	combout => \inst|inst1|inst|31~0_combout\);

-- Location: FF_X18_Y11_N31
\inst|inst1|inst|31\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst1|inst|ALT_INV_34~q\,
	d => \inst|inst1|inst|31~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst1|inst|31~q\);

-- Location: LCCOMB_X16_Y10_N30
\inst|inst2|inst|20\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst2|inst|20~combout\ = LCELL((\inst|inst2|inst|3~q\) # (!\inst|inst1|inst|31~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst1|inst|31~q\,
	datad => \inst|inst2|inst|3~q\,
	combout => \inst|inst2|inst|20~combout\);

-- Location: LCCOMB_X16_Y10_N6
\inst|inst2|inst|6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst2|inst|6~0_combout\ = !\inst|inst2|inst|6~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst2|inst|6~q\,
	combout => \inst|inst2|inst|6~0_combout\);

-- Location: FF_X16_Y10_N7
\inst|inst2|inst|6\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst2|inst|20~combout\,
	d => \inst|inst2|inst|6~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst2|inst|6~q\);

-- Location: LCCOMB_X14_Y10_N8
\inst|inst2|inst|5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst2|inst|5~0_combout\ = !\inst|inst2|inst|5~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst2|inst|5~q\,
	combout => \inst|inst2|inst|5~0_combout\);

-- Location: FF_X14_Y10_N9
\inst|inst2|inst|5\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst2|inst|ALT_INV_6~q\,
	d => \inst|inst2|inst|5~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst2|inst|5~q\);

-- Location: LCCOMB_X16_Y10_N28
\inst|inst2|inst|3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst2|inst|3~0_combout\ = (\inst|inst2|inst|6~q\ & (!\inst|inst2|inst|3~q\ & \inst|inst2|inst|5~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|inst2|inst|6~q\,
	datac => \inst|inst2|inst|3~q\,
	datad => \inst|inst2|inst|5~q\,
	combout => \inst|inst2|inst|3~0_combout\);

-- Location: FF_X16_Y10_N29
\inst|inst2|inst|3\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst1|inst|ALT_INV_31~q\,
	d => \inst|inst2|inst|3~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst2|inst|3~q\);

-- Location: LCCOMB_X6_Y9_N0
\inst|inst2|inst|7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|inst2|inst|7~0_combout\ = !\inst|inst2|inst|7~q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \inst|inst2|inst|7~q\,
	combout => \inst|inst2|inst|7~0_combout\);

-- Location: FF_X6_Y9_N1
\inst|inst2|inst|7\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \inst|inst2|inst|ALT_INV_3~q\,
	d => \inst|inst2|inst|7~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \inst|inst2|inst|7~q\);

-- Location: LCCOMB_X6_Y9_N18
inst1 : cycloneive_lcell_comb
-- Equation(s):
-- \inst1~combout\ = (\inst|inst1|inst|31~q\ & \inst|inst2|inst|7~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \inst|inst1|inst|31~q\,
	datad => \inst|inst2|inst|7~q\,
	combout => \inst1~combout\);

ww_B2_021 <= \B2_021~output_o\;

ww_pin_name1 <= \pin_name1~output_o\;

ww_pin_name2 <= \pin_name2~output_o\;
END structure;


